This invention relates to a phase comparator for a biphase coded signal including a preamble with code violation.
One form of data coding is known as biphase coding. In biphase coding, a signal epoch is divided into time slots by a clock, and one source data bit occupies a single time slot. Each source data bit may be represented by a two-cell doublet. Each coding doublet begins, and therefore also ends, with a transition. A source data bit one generates a transition between the two cells of the doublet, whereas a source data bit zero does not. Thus, a source data bit zero is represented either as the doublet zero zero or the doublet one one, while a source data bit one is represented either by the doublet one zero or the doublet zero one.
In order to recover data from a biphase coded signal, it is necessary first to extract clock information from the signal. The biphase signal (FIG. 1, waveform A) is first differentiated and rectified, by applying the biphase signal and a delayed version thereof to respective inputs of an exclusive OR gate 2, so as to produce a signal (waveform B) that has one pulse for each transition of the biphase coded signal. The resulting pulse train is applied to a non-retriggerable one-shot 4 having a shot duration equal to approximately 75% of the clock period. On the pulse representing the second transition of the first source data bit zero (and the first transition of the next source data bit), the one-shot is set and its output remains high for 75% of the next clock period. If the next source data bit is also zero, the one-shot is set by the pulse representing the transition at the end of that bit, and if the next source data bit is one, the one-shot filters out the pulse that occurs between the two cells of the doublet and is set again by the pulse representing the transition at the end of that source data bit. The output of the one-shot is therefore a pulse train at the data clock frequency and having a 75% duty cycle (FIG. 1, waveform C).
As also shown in FIG. 1, the output of the one-shot may be applied to one input of a phase comparator 6 that is connected in a phase lock loop that also includes a voltage-controlled oscillator (VCO) 8, a frequency divider 10 and an inverting integrating error amplifier 12, connected as shown. The frequency range of the output signal of the VCO includes four times the clock frequency and the frequency divider 10 divides the frequency of the output signal of the VCO 8 by a factor of four.
The phase comparator examines the phase difference between the input signal and the feedback signal provided by the VCO 8 and provides an error signal representative of the phase difference. The error signal acts through the error amplifier to keep the feedback signal synchronized to the input signal.
The phase comparator comprises two D flip-flops 20 and 24, each receiving a logical one at its D input. The flip-flop 20 receives the input signal fin (the output of one-shot 4) at its clock input, and the flip-flop 24 receives the feedback signal f.sub.fb provided by the VCO 8 and the frequency divider 10. The Q output of the flip-flop 20 is connected through an inverter 22 to the cathode of a diode 26, whose anode is connected to the error amplifier through a resistor 38, and the Q output of the flip-flop 24 is connected to the anode of a diode 28, whose cathode is connected to the error amplifier through a resistor 40. The Q outputs of the two flip-flops are connected as respective inputs to an AND gate 30, whose output is connected to the reset inputs of the flip-flops.
Operation of the phase comparator shown in FIG. 1 can be understood by considering the condition in which the feedback signal is at about the same frequency as the input signal but is not synchronized with the input signal. In this condition, a single clocking transition of the feedback signal will occur between each two successive clocking transitions of the input signal. If it is assumed that the two flip-flops are in the reset condition (both Q20 and Q24 are low) and that the next clocking transition that is received by the phase comparator is a transition of the input signal fin (FIG. 2A), flip-flop 20 is set high before flip-flop 24. During the time interval between the input signal transition and the subsequent feedback signal transition, the output of flip-flop 20 remains in the set condition while the output of flip-flop 24 remains in the reset condition. Consequently, inverter 22 pulls charge through diode 26 from the error amplifier during this time interval. Since the error amplifier is an inverting amplifier, the control voltage applied to the VCO 8 increases, so that the transitions of the feedback signal are advanced in time relative to what would happen if the control voltage remained constant. In this condition, the input signal f.sub.in is said to lead the feedback signal. When the clocking transition of the feedback signal is received by flip-flop 24, AND gate 30 resets both flip-flops and inverter 22 stops pulling charge from the error amplifier. Conversely, if the next clocking transition received by the comparator when both flip-flops are in the reset condition is a transition of the feedback signal (FIG. 2B), then flip-flop 24 pumps charge through diode 28 into the error amplifier during the time interval between the feedback signal's clocking transition and the subsequent transition of the input signal. The control voltage applied to the VCO decreases, so that the transitions of the feedback signal are retarded in time. The input signal is said to lag the feedback signal. In this fashion, the phase comparator operates to adjust the VCO to synchronize the output signal of the frequency divider with the input signal (FIG. 2C) and the phase lock loop produces a regenerated clock that is coherently related to the clock information in the biphase coded signal and can be applied to a data recovery flip-flop 14 to recover data from the biphase coded signal.
The conventional phase comparator shown in FIG. 2 has a capture range of almost +/-2 .pi. relative to the cycle of the feedback signal, i.e. the input signal can lead or lag the feedback signal by up to 2 .pi. and the phase comparator will still function in the manner described above. If the input signal is leading (or lagging) the feedback signal by an angle approaching 2 .pi., and the angle increases to 2 .pi.+.DELTA., the phase lock loop's behavior changes to treat the input signal as lagging (leading) the feedback signal by 2 .pi.-.DELTA..
The Audio Engineering Society/European Broadcasting Union datastream for digital audio data consists of a biphase coded signal in which each audio sample is represented by a subframe containing 32 time slots. The Audio Engineering Society and European Broadcasting Union standards do not prescribe the clock frequency of the biphase coded signal used for the digital audio datastream. In different applications, clock frequencies ranging from 1.792 MHz to 3.456 MHz are employed.
In accordance with the Audio Engineering Society/European Broadcasting Union standards, the first four time slots of each subframe constitute a preamble containing at least one occurrence of the three cell sequence zero zero zero or one one one. This brief departure from the usual biphase coding rules is known as a code violation. If the circuit shown in FIG. 1 is used to extract clock information from an AES/EBU signal, the code violation results in a momentary change in the frequency of the clock signal provided by the one-shot 4, and in pumping of excess charge into, or pulling of excess charge from, the error amplifier 4. So long as the time constant of the error amplifier exceeds the duration of the preamble, the code violation does not cause the phase lock loop to lose lock. Nevertheless, the code violation causes an increase in jitter, and this can affect the accuracy with which data is extracted.
A duty-cycle sensitive phase comparator may be used in the circuit shown in FIG. 1 instead of the edge sensitive phase comparator 6 to provide improved immunity to the code violation, but this measure is subject to the disadvantage that the capture range of a duty-cycle sensitive phase comparator is only +/-.pi. relative to the period of the feedback signal, so that if the input signal leads or lags the feedback signal by an angle greater than .pi. radians, the phase lock loop cannot acquire lock.
The VCO 8 might be implemented using a crystal controlled oscillator, in which case the gain of the VCO (in radians per volt) is sufficiently small that the change in the control voltage due to the code violation would not normally disturb operation of the phase lock loop to such an extent as to prevent accurate recovery of data. However, a phase lock loop with a crystal controlled oscillator cannot operate over the frequency range from 1.792 MHz to 3.456 MHz.
A VCO that is implemented using an LC oscillator can operate over a much wider range of frequencies than a crystal controlled oscillator, but the gain of such a VCO is substantially higher than that of a crystal controlled oscillator so that although the code violation might not cause the phase lock loop to lose lock with the input signal, the amount of jitter introduced by the violation could interfere with accurate data recovery.